CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 84.
161. lappuse
... reduce code size . Section 5 describes ET algorithms . Section 6 proposes new IA32 Echo instructions and presents the evaluation results . Section 7 discusses future work . Section 8 concludes the paper . 2. RELATED WORK There have been ...
... reduce code size . Section 5 describes ET algorithms . Section 6 proposes new IA32 Echo instructions and presents the evaluation results . Section 7 discusses future work . Section 8 concludes the paper . 2. RELATED WORK There have been ...
166. lappuse
... reduced as opposed to its average - case ex- ecution time . Unfortunately , existing custom instruction selection techniques based on average - case profile informa- tion may not reduce a task's WCET . We first develop an Integer Linear ...
... reduced as opposed to its average - case ex- ecution time . Unfortunately , existing custom instruction selection techniques based on average - case profile informa- tion may not reduce a task's WCET . We first develop an Integer Linear ...
180. lappuse
... reduced in order to support OS - level separation , which causes the system to run multiple OSs . In general , read - only data is often placed on ROMs to reduce the total memory requirement for RAMS or to shorten the boot time for the ...
... reduced in order to support OS - level separation , which causes the system to run multiple OSs . In general , read - only data is often placed on ROMs to reduce the total memory requirement for RAMS or to shorten the boot time for the ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
31 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx