CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.3. rezultāts no 30.
28. lappuse
... reconfiguration time penalties associated with general - purpose reconfigurable fabric . 2. BACKGROUND AND RELATED WORK In order to leverage the increasing relative performance , area , and power benefits of hardware vs. software ...
... reconfiguration time penalties associated with general - purpose reconfigurable fabric . 2. BACKGROUND AND RELATED WORK In order to leverage the increasing relative performance , area , and power benefits of hardware vs. software ...
243. lappuse
... reconfigurable hardware . In contrast to the compile - once - run - anywhere concept of virtual machines , reconfigurable applications lack portability and transparent SW / HW interfacing : applicability of accelerated hardware ...
... reconfigurable hardware . In contrast to the compile - once - run - anywhere concept of virtual machines , reconfigurable applications lack portability and transparent SW / HW interfacing : applicability of accelerated hardware ...
244. lappuse
... reconfigurable applications . chine code from bytecode ) is used nowadays , the future vir- tual machine should employ JiT synthesis ( producing FPGA configuration from bytecode ) to move any critical software section to reconfigurable ...
... reconfigurable applications . chine code from bytecode ) is used nowadays , the future vir- tual machine should employ JiT synthesis ( producing FPGA configuration from bytecode ) to move any critical software section to reconfigurable ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx