CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 4.
121. lappuse
... receiver [ 15 ] , a static periodic wireless application . It consists of three different tasks that are executed sequentially per time frame period , namely an FFT task , a task that performs unscrambling called Deinterleaver and an ...
... receiver [ 15 ] , a static periodic wireless application . It consists of three different tasks that are executed sequentially per time frame period , namely an FFT task , a task that performs unscrambling called Deinterleaver and an ...
282. lappuse
... receiver to the sender of the original message with the ACK bit set in the TCP header . Although " piggybacking " of these acknowledgements into into packets carrying other payload information is possible , in most cases there is no ...
... receiver to the sender of the original message with the ACK bit set in the TCP header . Although " piggybacking " of these acknowledgements into into packets carrying other payload information is possible , in most cases there is no ...
329. lappuse
... receiver unit of the packet , a 54 bit header carrying information about the packet and the payload ( variable number of bits ) , which are information for the upper layers . 3.2 The Bluetooth core implementation The Bluetooth core ...
... receiver unit of the packet , a 54 bit header carrying information about the packet and the payload ( variable number of bits ) , which are information for the upper layers . 3.2 The Bluetooth core implementation The Bluetooth core ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx