CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 77.
34. lappuse
... propose a new cell implementation for low - power set - associative TLBS . A low - power and high - performance TLB architecture has been proposed in [ 6 ] . A TLB organization is proposed that dynamically supports up to two pages per ...
... propose a new cell implementation for low - power set - associative TLBS . A low - power and high - performance TLB architecture has been proposed in [ 6 ] . A TLB organization is proposed that dynamically supports up to two pages per ...
38. lappuse
... proposed technique 76.5 to 0.18μ , 1.7V Vdd process technology by applying the same esti- mation methodology as the one utilized in CACTI . The power con- sumption of the few logic gates needed in the computation of the final CTT index ...
... proposed technique 76.5 to 0.18μ , 1.7V Vdd process technology by applying the same esti- mation methodology as the one utilized in CACTI . The power con- sumption of the few logic gates needed in the computation of the final CTT index ...
109. lappuse
... proposed DVFS policy for all benchmarks . Energy consumption is normalized to the energy consumption using the highest frequency ( without DVFS ) . The bar shows the normalized energy using our proposed DVFS . The dotted line shows the ...
... proposed DVFS policy for all benchmarks . Energy consumption is normalized to the energy consumption using the highest frequency ( without DVFS ) . The bar shows the normalized energy using our proposed DVFS . The dotted line shows the ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx