CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 17.
7. lappuse
... programmable and dynamically reconfigurable method of reusing hardware to implement physical layer processing . In this paper , we discuss trends in wireless platforms which are inherently convergence platforms . We also present the ...
... programmable and dynamically reconfigurable method of reusing hardware to implement physical layer processing . In this paper , we discuss trends in wireless platforms which are inherently convergence platforms . We also present the ...
67. lappuse
have applied this method specifically to create an environment for developing programmable platforms . 3.2 Multiple Views Methodology In Figure 4 , we illustrate our multiple views methodology . The labeled arrows indicate what a view ...
have applied this method specifically to create an environment for developing programmable platforms . 3.2 Multiple Views Methodology In Figure 4 , we illustrate our multiple views methodology . The labeled arrows indicate what a view ...
249. lappuse
... Programmable platforms are the best way of fulfilling today's and tomorrow's flexibility constraints , and tailoring them specifi- cally for the target application domain is the key to meet the per- formance demands with a good energy ...
... Programmable platforms are the best way of fulfilling today's and tomorrow's flexibility constraints , and tailoring them specifi- cally for the target application domain is the key to meet the per- formance demands with a good energy ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx