CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 82.
16. lappuse
... presented by Coelho and De Micheli [ 6 ] . The approach is based on the idea to calculate all possible schedules statically with respect to the control flow and all communications in order to select a pre- calculated schedule ...
... presented by Coelho and De Micheli [ 6 ] . The approach is based on the idea to calculate all possible schedules statically with respect to the control flow and all communications in order to select a pre- calculated schedule ...
137. lappuse
... presented in this paper , e.g. a face detection system was implemented on a reconfigurable platform , with area results requiring multiple FPGA boards [ 3 ] . An ASIC implementation of a fairly complex face detection algorithm was presented ...
... presented in this paper , e.g. a face detection system was implemented on a reconfigurable platform , with area results requiring multiple FPGA boards [ 3 ] . An ASIC implementation of a fairly complex face detection algorithm was presented ...
143. lappuse
... presented in [ 4 ] . This work presented a core power evaluation technique that divided the function of the cores into instructions and performed estimation using instruction level power models . The assumption made in this approach was ...
... presented in [ 4 ] . This work presented a core power evaluation technique that divided the function of the cores into instructions and performed estimation using instruction level power models . The assumption made in this approach was ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx