CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 78.
39. lappuse
... present a formidable bottleneck to accelerating embedded applications , particularly data bandwidth . for multiple - issue VLIW processors . Providing an efficient ASIP data cache solution requires that the cache design be tailored to ...
... present a formidable bottleneck to accelerating embedded applications , particularly data bandwidth . for multiple - issue VLIW processors . Providing an efficient ASIP data cache solution requires that the cache design be tailored to ...
67. lappuse
... present ( out ) ) ) A ( Vin , e inputs . ( assigns ( in , oa ) present ( in . ) ) ) ) ) AYSW & SW . ( SW , ( Yout , e outputs ( assigns ( out , sw . ) present ( out ) ) ) A ( vin , e inputs . ( assignsin , sw ) A present ( in ...
... present ( out ) ) ) A ( Vin , e inputs . ( assigns ( in , oa ) present ( in . ) ) ) ) ) AYSW & SW . ( SW , ( Yout , e outputs ( assigns ( out , sw . ) present ( out ) ) ) A ( vin , e inputs . ( assignsin , sw ) A present ( in ...
328. lappuse
... present paper , we propose a simple method , based on redundant stimuli filtering . It allows reducing execution time of testbenches with random stimuli , without resorting to complex algorithms . This filtering technique is based on ...
... present paper , we propose a simple method , based on redundant stimuli filtering . It allows reducing execution time of testbenches with random stimuli , without resorting to complex algorithms . This filtering technique is based on ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
31 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx