CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.3. rezultāts no 56.
61. lappuse
... ports and as soon as the second port is connected to a channel , a connection between the two port data structures is made by setting up remote pointers between them . A task may not be started before all active ports are connected . When a ...
... ports and as soon as the second port is connected to a channel , a connection between the two port data structures is made by setting up remote pointers between them . A task may not be started before all active ports are connected . When a ...
85. lappuse
... ports . The router is clocked at 20 MHz , offering a bandwidth of 640 Mbps per port . Fig.7 describes the evolution of the power consumption and of the area overhead for different choices of granularity for a 32 bit- wide port . It ...
... ports . The router is clocked at 20 MHz , offering a bandwidth of 640 Mbps per port . Fig.7 describes the evolution of the power consumption and of the area overhead for different choices of granularity for a 32 bit- wide port . It ...
264. lappuse
... port ) , and Write ( to write the address to a RTL port ) . While the first service is provided by a SW element , the other ones are provided by HW ports . SW API ( TLM ) I / O Element ReadAdr Device Driver Block UnBlock Low Read ...
... port ) , and Write ( to write the address to a RTL port ) . While the first service is provided by a SW element , the other ones are provided by HW ports . SW API ( TLM ) I / O Element ReadAdr Device Driver Block UnBlock Low Read ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx