CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.3. rezultāts no 76.
179. lappuse
... platform which employs Linux on a chip multiprocessor in order to achieve higher performance and more secure execution environment on OSS with high functionality . We call this platform FIDES . It forms a domain on each processor , so ...
... platform which employs Linux on a chip multiprocessor in order to achieve higher performance and more secure execution environment on OSS with high functionality . We call this platform FIDES . It forms a domain on each processor , so ...
182. lappuse
... platform mechanisms , which include the processor - level separation , offers the best security . In other words , this platform is more resilient to the attacks which consume the system resources , such as CPU time or memory . Further ...
... platform mechanisms , which include the processor - level separation , offers the best security . In other words , this platform is more resilient to the attacks which consume the system resources , such as CPU time or memory . Further ...
183. lappuse
... platform , which employs Linux on a chip multiprocessor , could guarantee security in executing downloaded native ... platform with multi - grained separation mechanisms is more secure than other platforms , such as software - only ...
... platform , which employs Linux on a chip multiprocessor , could guarantee security in executing downloaded native ... platform with multi - grained separation mechanisms is more secure than other platforms , such as software - only ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx