CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.3. rezultāts no 42.
322. lappuse
... PHASE CLASSIFICATION In this section we discuss phase behavior , code signatures , and we explain how the dynamic phase classifier works as the program executes . Our work builds upon program phase analysis techniques presented in [ 14 ...
... PHASE CLASSIFICATION In this section we discuss phase behavior , code signatures , and we explain how the dynamic phase classifier works as the program executes . Our work builds upon program phase analysis techniques presented in [ 14 ...
323. lappuse
... phase ID prediction is used . This approach is used to predict the phase ID ( phase signature table entry ) for the next interval of execution . We examined several values for n , and from our experiments we concluded that RLE - 2 ...
... phase ID prediction is used . This approach is used to predict the phase ID ( phase signature table entry ) for the next interval of execution . We examined several values for n , and from our experiments we concluded that RLE - 2 ...
326. lappuse
... phase analysis to guide collection of application profiles ( basic block counts , hot path execution , etc ) from remote applications running on energy and perfor- mance constrained devices . They also use dynamic phase clas- sification ...
... phase analysis to guide collection of application profiles ( basic block counts , hot path execution , etc ) from remote applications running on energy and perfor- mance constrained devices . They also use dynamic phase clas- sification ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx