CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 10.
11. lappuse
... Peripherals General Purpose O RF Control Derial ( SP 12C ) Timer O TX Data RX Data Interface Memory Interface ( Synchronous and Asynchronous ) 10-50EH REF TAP UTAD Part Dock Generation b & Dula Mam K Muti Part Memory DSP Smart Cand Byn ...
... Peripherals General Purpose O RF Control Derial ( SP 12C ) Timer O TX Data RX Data Interface Memory Interface ( Synchronous and Asynchronous ) 10-50EH REF TAP UTAD Part Dock Generation b & Dula Mam K Muti Part Memory DSP Smart Cand Byn ...
142. lappuse
... peripherals in a SOC . With the presence of complex cores in current day embedded system - on - chip devices , the problem of complete system level power estimation is gaining significance . Transaction level models for SoCs are gaining ...
... peripherals in a SOC . With the presence of complex cores in current day embedded system - on - chip devices , the problem of complete system level power estimation is gaining significance . Transaction level models for SoCs are gaining ...
265. lappuse
... Peripherals tasks include performing reads / writes data from / to files , combining the processed parts of the image , etc. VProc ( TLM ) SW DMA + Peripherals ( RTL ) HW Execution Environment ( TLM ) VLC ( TLM ) SW Figure 8. Abstract ...
... Peripherals tasks include performing reads / writes data from / to files , combining the processed parts of the image , etc. VProc ( TLM ) SW DMA + Peripherals ( RTL ) HW Execution Environment ( TLM ) VLC ( TLM ) SW Figure 8. Abstract ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx