CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 84.
6. lappuse
... PERFORMANCE With the focus moving away from the microprocessor core itself and single thread performance ( because it is " good enough " and too expensive to grow substantially ) , more emphasis will be put on optimizing the number of ...
... PERFORMANCE With the focus moving away from the microprocessor core itself and single thread performance ( because it is " good enough " and too expensive to grow substantially ) , more emphasis will be put on optimizing the number of ...
225. lappuse
Efficient Performance Analysis of Asynchronous Systems Based on Periodicity systems that exhibit regular architectures . In contrast , the. Peggy B. McGee Steven M. Nowick . Department of Computer Science Columbia University New York ...
Efficient Performance Analysis of Asynchronous Systems Based on Periodicity systems that exhibit regular architectures . In contrast , the. Peggy B. McGee Steven M. Nowick . Department of Computer Science Columbia University New York ...
241. lappuse
... performance using these optimizations . The results demonstrate 13 % to 30 % performance improvement in SimpleScalar . MIPS 14 12 Simplescalar I SAM SAM + IIF 20 10 8 9 Figure 13 and Figure 14 show the performance of Base Simulator for ...
... performance using these optimizations . The results demonstrate 13 % to 30 % performance improvement in SimpleScalar . MIPS 14 12 Simplescalar I SAM SAM + IIF 20 10 8 9 Figure 13 and Figure 14 show the performance of Base Simulator for ...
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Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx