CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 37.
288. lappuse
... partitioning tool can obtain the majority of speedup by implementing the several most frequent loops in hardware . However , the profiling results shown in Table 1 for the H.264 decoder show that the several most frequent regions are ...
... partitioning tool can obtain the majority of speedup by implementing the several most frequent loops in hardware . However , the profiling results shown in Table 1 for the H.264 decoder show that the several most frequent regions are ...
289. lappuse
... partitioning is competitive with C- level partitioning and that simple rewrites of the original code can improve speedups for both binary partitioning and C - level partitioning . 2 2 2 2 2 2 2 3 3 3 8 = 3 4 5 Number of Functions in ...
... partitioning is competitive with C- level partitioning and that simple rewrites of the original code can improve speedups for both binary partitioning and C - level partitioning . 2 2 2 2 2 2 2 3 3 3 8 = 3 4 5 Number of Functions in ...
290. lappuse
... partitioning . The increased overall application speedups from rewriting the code are shown in Figure 2 for both binary partitioning and C - level partitioning . The speedups for binary partitioning and C- level partitioning were almost ...
... partitioning . The increased overall application speedups from rewriting the code are shown in Figure 2 for both binary partitioning and C - level partitioning . The speedups for binary partitioning and C- level partitioning were almost ...
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx