CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 31.
280. lappuse
... packet reception and storage in the packet data memory sub - system , the ( multi - processor ) CPU cluster takes control over the packet handling . This includes determining the sequence in which dedicated co - processors and hardware ...
... packet reception and storage in the packet data memory sub - system , the ( multi - processor ) CPU cluster takes control over the packet handling . This includes determining the sequence in which dedicated co - processors and hardware ...
282. lappuse
... packet , which is sufficient for QoS or DiffServ forwarding on the entire link capacity . With respect to the two FlexPath alternatives , the following observations can be made : • For b = 0 % ( i.e. all packets traverse the CPU cluster ) ...
... packet , which is sufficient for QoS or DiffServ forwarding on the entire link capacity . With respect to the two FlexPath alternatives , the following observations can be made : • For b = 0 % ( i.e. all packets traverse the CPU cluster ) ...
284. lappuse
... packet header validity checking , source , destination address extraction , protocol stack determination , ARP , ICMP and TCP / ACK packet flagging . The Pre - Processor aligns all pertinent header fields onto CPU word boundaries and ...
... packet header validity checking , source , destination address extraction , protocol stack determination , ARP , ICMP and TCP / ACK packet flagging . The Pre - Processor aligns all pertinent header fields onto CPU word boundaries and ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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