CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 85.
51. lappuse
... overhead while requiring the same amount of buffer memory as modulo buffering . Considering the sample copy overhead , shift buffering is applicable when memory size is more crucial than performance overhead , and the shifting overhead ...
... overhead while requiring the same amount of buffer memory as modulo buffering . Considering the sample copy overhead , shift buffering is applicable when memory size is more crucial than performance overhead , and the shifting overhead ...
122. lappuse
... overhead compared to nominal design ( DAB ) Panel 1 What will System Level Design be When It. Application level adaptation 80 % 70 % 60 % Clock level adaptation Corner - point design 50 % 40 % 30 % 20 % 10 % 0 % 0.754 0.814 0.91 ...
... overhead compared to nominal design ( DAB ) Panel 1 What will System Level Design be When It. Application level adaptation 80 % 70 % 60 % Clock level adaptation Corner - point design 50 % 40 % 30 % 20 % 10 % 0 % 0.754 0.814 0.91 ...
319. lappuse
... Overhead ( cmds / sec ) Figure 6 : Loading overhead vs. packet size 9 876 5 4 3 2 - Figure 5 : Delay of loading commands vs. communication speed fit entirely in RAM as opposed to loading from the much slower flash memory , the script in ...
... Overhead ( cmds / sec ) Figure 6 : Loading overhead vs. packet size 9 876 5 4 3 2 - Figure 5 : Delay of loading commands vs. communication speed fit entirely in RAM as opposed to loading from the much slower flash memory , the script in ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
31 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx