CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.3. rezultāts no 75.
113. lappuse
... obtained at run - time . They represent an on- line improvement of the static bounds . The dynamic bounds are obtained using the workload history . Depending on the nature of the workload variation , these bounds can be much tighter ...
... obtained at run - time . They represent an on- line improvement of the static bounds . The dynamic bounds are obtained using the workload history . Depending on the nature of the workload variation , these bounds can be much tighter ...
116. lappuse
... obtained by the " oracle " DPM with instantaneous on - off switching of PE2 running at a fixed fsafe . The corresponding graph is shown in Figure 4 ( b ) with a dotted line and is labelled as safe_iDPM . By inspecting the plots in ...
... obtained by the " oracle " DPM with instantaneous on - off switching of PE2 running at a fixed fsafe . The corresponding graph is shown in Figure 4 ( b ) with a dotted line and is labelled as safe_iDPM . By inspecting the plots in ...
140. lappuse
... obtained by extracting the critical cycle in each class . 6. EXPERIMENTAL RESULTS We have evaluated our proposed designs on a Xilinx ML310 development board . 6.1 Design Space Exploration As it can be seen from Table 2 , the system ...
... obtained by extracting the critical cycle in each class . 6. EXPERIMENTAL RESULTS We have evaluated our proposed designs on a Xilinx ML310 development board . 6.1 Design Space Exploration As it can be seen from Table 2 , the system ...
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A Core Flight Software System | 13 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx