CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 24.
213. lappuse
... multiplier units . Larger multiplier units are required for cryptography and error correction circuits for more secure and reliable transmissions over highly insecure and / or noisy channels in networking and multimedia applications ...
... multiplier units . Larger multiplier units are required for cryptography and error correction circuits for more secure and reliable transmissions over highly insecure and / or noisy channels in networking and multimedia applications ...
215. lappuse
... Multiplier Architectures When constructing large - width multiplier data paths , a first - cut approach is to specify a " monolithic ” ( i.e. , flat ) multiplier that takes two large word operands and multiplies them to generate partial ...
... Multiplier Architectures When constructing large - width multiplier data paths , a first - cut approach is to specify a " monolithic ” ( i.e. , flat ) multiplier that takes two large word operands and multiplies them to generate partial ...
216. lappuse
... multipliers . We can take advantage of the high performance and resource efficiency of the built - in hardware multipliers in many Xilinx Virtex - II® chips . The Xilinx Vertex - II FPGA comes with embedded multiplier blocks that can do ...
... multipliers . We can take advantage of the high performance and resource efficiency of the built - in hardware multipliers in many Xilinx Virtex - II® chips . The Xilinx Vertex - II FPGA comes with embedded multiplier blocks that can do ...
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx