CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 61.
8. lappuse
... multiple hardware elements in software . Tier - 2 , Software Defined Radio ( SDR ) , implements modulation and baseband processing in software but allows for multiple frequency fixed function RF hardware . Tier - 3 , Ideal Software ...
... multiple hardware elements in software . Tier - 2 , Software Defined Radio ( SDR ) , implements modulation and baseband processing in software but allows for multiple frequency fixed function RF hardware . Tier - 3 , Ideal Software ...
39. lappuse
... multiple - issue VLIW processors . Providing an efficient ASIP data cache solution requires that the cache design be tailored to the target application . Multiple caches or caches with multiple ports allow simultaneous parallel access ...
... multiple - issue VLIW processors . Providing an efficient ASIP data cache solution requires that the cache design be tailored to the target application . Multiple caches or caches with multiple ports allow simultaneous parallel access ...
40. lappuse
... multiple caches of different types each with different sized banks . Grun et al . have produced excellent work on memory architecture exploration in [ 5 ] culminating in a tool called APEX . This work considers the entire memory of an ...
... multiple caches of different types each with different sized banks . Grun et al . have produced excellent work on memory architecture exploration in [ 5 ] culminating in a tool called APEX . This work considers the entire memory of an ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx