CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 11.
73. lappuse
... algorithm for the energy minimization problem is proposed in [ 27 ] . The algorithm first allocates more slack to those tasks which have a larger impact on energy consumption and performance . A level - based scheduling mechanism is ...
... algorithm for the energy minimization problem is proposed in [ 27 ] . The algorithm first allocates more slack to those tasks which have a larger impact on energy consumption and performance . A level - based scheduling mechanism is ...
92. lappuse
... minimization in systems with embedded processors . In Proc . DATE 2002 , pp . 449-450 , 2002 . [ 2 ] M. Chen and M. L. Fowler . The importance of data compression for energy efficiency in sensor networks . In Proc . 2003 Conference on ...
... minimization in systems with embedded processors . In Proc . DATE 2002 , pp . 449-450 , 2002 . [ 2 ] M. Chen and M. L. Fowler . The importance of data compression for energy efficiency in sensor networks . In Proc . 2003 Conference on ...
205. lappuse
... minimization frees up more unit cells for sample collection and preparation . Moreover , we can further enhance the synthesis methodology by unifying operation scheduling , resource binding , and module placement together ; Figure 4 ...
... minimization frees up more unit cells for sample collection and preparation . Moreover , we can further enhance the synthesis methodology by unifying operation scheduling , resource binding , and module placement together ; Figure 4 ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx