CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 66.
296. lappuse
... methodology . We then mapped the H.264 modules onto the WaveScalar dataflow architecture with the help of a simulated annealing - based placement algorithm that uses the data transfer matrix to place blocks that communicate a lot close ...
... methodology . We then mapped the H.264 modules onto the WaveScalar dataflow architecture with the help of a simulated annealing - based placement algorithm that uses the data transfer matrix to place blocks that communicate a lot close ...
304. lappuse
... methodology clearly outperforms commercial compilers providing an additional 75 % speedup on average . The rest of the paper is organized as follows . Section 2 describes the algorithms that can potentially benefit form the methodology ...
... methodology clearly outperforms commercial compilers providing an additional 75 % speedup on average . The rest of the paper is organized as follows . Section 2 describes the algorithms that can potentially benefit form the methodology ...
308. lappuse
... methodology to efficiently exploit short vector parallelism from the external loop in loop nests that process 2D arrays . These algorithms are extensively used in modern multimedia , networking or signal processing embedded systems ...
... methodology to efficiently exploit short vector parallelism from the external loop in loop nests that process 2D arrays . These algorithms are extensively used in modern multimedia , networking or signal processing embedded systems ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx