CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.3. rezultāts no 77.
52. lappuse
... method requires large size buffers and the modulo buffering method needs run - time overhead of buffer index computation . This paper proposes a new efficient buffer management technique called shift buffering . The shift buffering method ...
... method requires large size buffers and the modulo buffering method needs run - time overhead of buffer index computation . This paper proposes a new efficient buffer management technique called shift buffering . The shift buffering method ...
205. lappuse
... method . A combinational optimization method , such as parallel recombinative simulated annealing ( PRSA ) , can be used for this integrated synthesis method [ 23 ] . All three tasks , i.e. , resource binding , scheduling , and ...
... method . A combinational optimization method , such as parallel recombinative simulated annealing ( PRSA ) , can be used for this integrated synthesis method [ 23 ] . All three tasks , i.e. , resource binding , scheduling , and ...
246. lappuse
... Method Information I ; a Configure FPGA Mapping Thread VMW Patched Java Bytecode Java Bridge Class TH JVM JNI HW Method Accelerator n Retrieve Parameters Wait Callback FPGA EXECUTE ( ) Return and Synch Coprocessor Finished Callback ...
... Method Information I ; a Configure FPGA Mapping Thread VMW Patched Java Bytecode Java Bridge Class TH JVM JNI HW Method Accelerator n Retrieve Parameters Wait Callback FPGA EXECUTE ( ) Return and Synch Coprocessor Finished Callback ...
Saturs
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx