CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 87.
88. lappuse
... Memory Local Memory Local Local Memory Memory ( a ) ( ၁ ) Figure 1 : Components of the proposed approach . This paper proposes a data compression based approach to re- duce the negative impact of the second option mentioned above ...
... Memory Local Memory Local Local Memory Memory ( a ) ( ၁ ) Figure 1 : Components of the proposed approach . This paper proposes a data compression based approach to re- duce the negative impact of the second option mentioned above ...
90. lappuse
... memory space al- located for each processor . As mentioned earlier , although the available on - chip memory space is divided among the processors equally , it is possible to modify our formulation to reflect a non- uniform distribution ...
... memory space al- located for each processor . As mentioned earlier , although the available on - chip memory space is divided among the processors equally , it is possible to modify our formulation to reflect a non- uniform distribution ...
232. lappuse
... memory dependency representation 2. Memory redundancy elimination : Kolson [ 13 ] uses Tree Height Reduction to consider memory access latencies and redun- dancies in forming a schedule . Recent work by Stitt [ 23 ] shows how words ...
... memory dependency representation 2. Memory redundancy elimination : Kolson [ 13 ] uses Tree Height Reduction to consider memory access latencies and redun- dancies in forming a schedule . Recent work by Stitt [ 23 ] shows how words ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx