CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.3. rezultāts no 53.
120. lappuse
... measurement phase the process variation controller sends test vectors to each individual memory and the monitors measure their energy consumption per access and the access delay . The maximum energy consumption and delay are calculated ...
... measurement phase the process variation controller sends test vectors to each individual memory and the monitors measure their energy consumption per access and the access delay . The maximum energy consumption and delay are calculated ...
188. lappuse
... measurements performed for the ARM7TDMI processor core executing the DES encryption . From these results , we can ... measurement and is controlled by a current injection control module . Fig . 5 shows the current simulation results that ...
... measurements performed for the ARM7TDMI processor core executing the DES encryption . From these results , we can ... measurement and is controlled by a current injection control module . Fig . 5 shows the current simulation results that ...
320. lappuse
... measurements . It consists of a broadband generator , laser modulator , and detector as shown in Fig . 9. It also includes the FreeScale MC9S12NE64 16 - bit MCU with an integrated 10/100 Mbps Ethernet controller . The MCU controls the ...
... measurements . It consists of a broadband generator , laser modulator , and detector as shown in Fig . 9. It also includes the FreeScale MC9S12NE64 16 - bit MCU with an integrated 10/100 Mbps Ethernet controller . The MCU controls the ...
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Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx