CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 50.
9. lappuse
... language implementations that specify integer modulo modulo arithmetic . Therefore , most DSPs have been programmed using assembly language . Multimedia adds additional requirements to the convergence processors . Video , in particular ...
... language implementations that specify integer modulo modulo arithmetic . Therefore , most DSPs have been programmed using assembly language . Multimedia adds additional requirements to the convergence processors . Video , in particular ...
10. lappuse
... language constructs and this resulted in compiler scheduling hazards . Other solutions , which attempted to convey side - effect free instructions , have been proposed . These solutions all introduced architectural dependent ...
... language constructs and this resulted in compiler scheduling hazards . Other solutions , which attempted to convey side - effect free instructions , have been proposed . These solutions all introduced architectural dependent ...
99. lappuse
... language interoperability , code access security , memory , management and garbage collection , thread facilities . .NET executables are encoded in a Common Intermediate Language ( CIL , sometimes called MSIL by Microsoft ) , an in ...
... language interoperability , code access security , memory , management and garbage collection , thread facilities . .NET executables are encoded in a Common Intermediate Language ( CIL , sometimes called MSIL by Microsoft ) , an in ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx