CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 79.
161. lappuse
... instruction to compress Java bytecodes . They use a form of " sequential Echo " instruction , allowing call , return , and nested Echo instructions inside Echo regions . The Echo instructions reduced the size of bytecode by about 30 ...
... instruction to compress Java bytecodes . They use a form of " sequential Echo " instruction , allowing call , return , and nested Echo instructions inside Echo regions . The Echo instructions reduced the size of bytecode by about 30 ...
162. lappuse
instructions in an Echo region should be a target of a branch instruction , as the whole Echo region will be replaced by an Echo instruction and the branch target will no longer exist afterward . Furthermore , internal control flow ...
instructions in an Echo region should be a target of a branch instruction , as the whole Echo region will be replaced by an Echo instruction and the branch target will no longer exist afterward . Furthermore , internal control flow ...
240. lappuse
... Instruction Fetch ( IIF ) In any instruction - set simulator , as in real hardware , the program counter indicates the address of the instruction that must be executed next . Figure 8 shows the simulation loop : the opcode ( or the ...
... Instruction Fetch ( IIF ) In any instruction - set simulator , as in real hardware , the program counter indicates the address of the instruction that must be executed next . Figure 8 shows the simulation loop : the opcode ( or the ...
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx