CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 85.
4. lappuse
... increase as the transistor switching speed increased , while switching power density remained approximately constant . Unfortunately , scaling also results in exponential increases in leakage power , and by the 90nm node , this leakage ...
... increase as the transistor switching speed increased , while switching power density remained approximately constant . Unfortunately , scaling also results in exponential increases in leakage power , and by the 90nm node , this leakage ...
93. lappuse
... increases packaging and cooling costs , size , and energy consumption . This paper presents CRAMES , an efficient software - based RAM compression technique for embedded sys- tems . The goal of CRAMES is to dramatically increase ...
... increases packaging and cooling costs , size , and energy consumption . This paper presents CRAMES , an efficient software - based RAM compression technique for embedded sys- tems . The goal of CRAMES is to dramatically increase ...
288. lappuse
... increase parallelism if dependencies were not violated . When possible , we copied data from main memory into multiple FPGA memories to increase the memory bandwidth during computational kernels that needed fast access to multiple array ...
... increase parallelism if dependencies were not violated . When possible , we copied data from main memory into multiple FPGA memories to increase the memory bandwidth during computational kernels that needed fast access to multiple array ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx