CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 78.
242. lappuse
... improve the performance ( up to 89 % ) of the simulator . Our techniques improved the performance ( up to 30 % ) of Simplescalar , a widely used interpretive simulator , which does not use any recent optimizations . 5. Conclusions ...
... improve the performance ( up to 89 % ) of the simulator . Our techniques improved the performance ( up to 30 % ) of Simplescalar , a widely used interpretive simulator , which does not use any recent optimizations . 5. Conclusions ...
247. lappuse
... improves performance : no user action is required . 300 6. EXPERIMENTS The measurement results refer to an embedded ... improve performance and ex- ms 500 400 200 300 150 ms 200 100 100 16KB 32KB Input Data Size ( a ) IDEA 50 32KB Input ...
... improves performance : no user action is required . 300 6. EXPERIMENTS The measurement results refer to an embedded ... improve performance and ex- ms 500 400 200 300 150 ms 200 100 100 16KB 32KB Input Data Size ( a ) IDEA 50 32KB Input ...
289. lappuse
... improve speedups for both binary partitioning and C - level partitioning . 2 2 2 2 2 2 2 3 3 3 8 = 3 4 5 Number of ... Improved alias analysis could allow for data to be fetched by the FPGA much earlier and in some cases the data could ...
... improve speedups for both binary partitioning and C - level partitioning . 2 2 2 2 2 2 2 3 3 3 8 = 3 4 5 Number of ... Improved alias analysis could allow for data to be fetched by the FPGA much earlier and in some cases the data could ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx