CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 31.
137. lappuse
... exploration . In contrast , previous develop- ment of synchronous graphs has focused on their use as an intermediate representation in automated tools [ 6 ] ) . We show how for application / domain - specific design , the system ...
... exploration . In contrast , previous develop- ment of synchronous graphs has focused on their use as an intermediate representation in automated tools [ 6 ] ) . We show how for application / domain - specific design , the system ...
273. lappuse
... exploration framework to build efficient FPGA multiprocessors for a target application . Our main contribution is a tool based on Integer Linear Programming to explore micro - architectures and allocate application tasks to maximize ...
... exploration framework to build efficient FPGA multiprocessors for a target application . Our main contribution is a tool based on Integer Linear Programming to explore micro - architectures and allocate application tasks to maximize ...
277. lappuse
... exploration , we use CPLEX [ 2 ] as our ILP solver . During the exploration we select the best design based on the ILP results and synthesize it to verify performance . Ver- ification may fail because we do not consider routing detail ...
... exploration , we use CPLEX [ 2 ] as our ILP solver . During the exploration we select the best design based on the ILP results and synthesize it to verify performance . Ver- ification may fail because we do not consider routing detail ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx