CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 83.
23. lappuse
... example , suppose we want to map DFG of Figure 4 on datapath of Figure 5. Operation >> can read the result of operation + in two ways . If we schedule operation on U2 and store the result in register file RF , then operation >> must be ...
... example , suppose we want to map DFG of Figure 4 on datapath of Figure 5. Operation >> can read the result of operation + in two ways . If we schedule operation on U2 and store the result in register file RF , then operation >> must be ...
91. lappuse
... EXAMPLE In this section , we give an example showing the effectiveness of our approach . An example data access pattern for a case with 4 processors , 6 steps and 12 data blocks is given in Table 3. We assume , for the sake of ...
... EXAMPLE In this section , we give an example showing the effectiveness of our approach . An example data access pattern for a case with 4 processors , 6 steps and 12 data blocks is given in Table 3. We assume , for the sake of ...
149. lappuse
... example , dynamic partitioning for re- configurable hardware selects the regions of the binary or source code to be sent to hardware modules [ 14 ] [ 15 ] . Other approaches are for reducing energy consumption by dynamic resource ...
... example , dynamic partitioning for re- configurable hardware selects the regions of the binary or source code to be sent to hardware modules [ 14 ] [ 15 ] . Other approaches are for reducing energy consumption by dynamic resource ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx