CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 76.
95. lappuse
... evaluated existing data compression algorithms that span a range of compression ra- tios and execution times : bzip2 ... evaluate compres- sion algorithms : resource map allocator ( rm ) , power - of - two freel- ists ( p2fl ) , McKusick ...
... evaluated existing data compression algorithms that span a range of compression ra- tios and execution times : bzip2 ... evaluate compres- sion algorithms : resource map allocator ( rm ) , power - of - two freel- ists ( p2fl ) , McKusick ...
182. lappuse
... evaluate these effects numerically . Instead , we evaluate the load time of a policy file . It has a great effect on reducing the boot time . This can be seen in Figure 7 , where the number of rules in a policy file is along the ...
... evaluate these effects numerically . Instead , we evaluate the load time of a policy file . It has a great effect on reducing the boot time . This can be seen in Figure 7 , where the number of rules in a policy file is along the ...
308. lappuse
... evaluated on a set of FIR fil- ters independently applied to several signals . In a future work we plan to extend the ... evaluate our methodology on different computing platforms in order to analyze the impact of some architectural ...
... evaluated on a set of FIR fil- ters independently applied to several signals . In a future work we plan to extend the ... evaluate our methodology on different computing platforms in order to analyze the impact of some architectural ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx