CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 32.
127. lappuse
... ESTIMATION COPROCESSOR Motion estimation is one of the time - critical tasks in the application algorithms . Apart from the typical sum - of - absolute- difference operations performed at pixel level , the combination of the required ...
... ESTIMATION COPROCESSOR Motion estimation is one of the time - critical tasks in the application algorithms . Apart from the typical sum - of - absolute- difference operations performed at pixel level , the combination of the required ...
142. lappuse
... estimation have focused on the processor , while there are very few that address power consumption of peripherals in a SOC . With the presence of complex cores in current day embedded system - on - chip devices , the problem of complete ...
... estimation have focused on the processor , while there are very few that address power consumption of peripherals in a SOC . With the presence of complex cores in current day embedded system - on - chip devices , the problem of complete ...
143. lappuse
... estimation approach with an example . Sections 5 and 6 , describe the power characterization approach and our system level transaction based power estimation technique . Finally section 7 , presents experimental results followed by a ...
... estimation approach with an example . Sections 5 and 6 , describe the power characterization approach and our system level transaction based power estimation technique . Finally section 7 , presents experimental results followed by a ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx