CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 93.
49. lappuse
... energy due to accessing off- chip memory and the energy_uP_stall is the energy consumed when the microprocessor is stalled to wait for the memory system to provide an instruction . energy_cache_block_fill is the energy for refilling a ...
... energy due to accessing off- chip memory and the energy_uP_stall is the energy consumed when the microprocessor is stalled to wait for the memory system to provide an instruction . energy_cache_block_fill is the energy for refilling a ...
109. lappuse
... Energy consumption is normalized to energy using the highest frequency ( 1GHz ) . The bar represents the normalized energy using our proposed DVFS . The dotted line represents the normalized optimal energy consumption . The dashed line ...
... Energy consumption is normalized to energy using the highest frequency ( 1GHz ) . The bar represents the normalized energy using our proposed DVFS . The dotted line represents the normalized optimal energy consumption . The dashed line ...
325. lappuse
... Energy Normalized Energy Normalized Energy Normalized Energy 0.95 0.9 0.85 0.8 0.75 0.7 0.65 0.95 0.9 0.85 0.8 0.75 0.7 0.65 1 0.98 0.96 0.94 0.92 0.9 0.88 0.86 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 Interval number 50 90 ...
... Energy Normalized Energy Normalized Energy Normalized Energy 0.95 0.9 0.85 0.8 0.75 0.7 0.65 0.95 0.9 0.85 0.8 0.75 0.7 0.65 1 0.98 0.96 0.94 0.92 0.9 0.88 0.86 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 Interval number 50 90 ...
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx