CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 83.
93. lappuse
... embedded systems . Increas- ing memory often increases packaging and cooling costs , size , and energy consumption . This paper presents CRAMES , an efficient software - based RAM compression technique for embedded sys- tems . The goal ...
... embedded systems . Increas- ing memory often increases packaging and cooling costs , size , and energy consumption . This paper presents CRAMES , an efficient software - based RAM compression technique for embedded sys- tems . The goal ...
94. lappuse
... embedded system RAM requirements and power consumption . However , they require changes to the under- İying hardware and thus cannot be easily incorporated into existing embedded systems . Most previous work on software - based memory ...
... embedded system RAM requirements and power consumption . However , they require changes to the under- İying hardware and thus cannot be easily incorporated into existing embedded systems . Most previous work on software - based memory ...
291. lappuse
... embedded applications , these architectures typically perform control- intensive tasks in a System - on - Chip ( SoC ) design . But they are significantly inefficient for data - intensive tasks such as video encoding / decoding ...
... embedded applications , these architectures typically perform control- intensive tasks in a System - on - Chip ( SoC ) design . But they are significantly inefficient for data - intensive tasks such as video encoding / decoding ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx