CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.3. rezultāts no 59.
151. lappuse
... elements in state " 4 " should move to state " 1 " first , then if N1 is not satisfied , elements from state " 2 " should make transitions , and so on . This is a set of constraints for the elements of type R1 which are N1 in number ...
... elements in state " 4 " should move to state " 1 " first , then if N1 is not satisfied , elements from state " 2 " should make transitions , and so on . This is a set of constraints for the elements of type R1 which are N1 in number ...
264. lappuse
... elements and services definition as well as their implementation . SDG Generator - Tool that generates the elements / services dependency graph for the required adaptation . As HW / SW / Functional interfaces are modeled in the same way ...
... elements and services definition as well as their implementation . SDG Generator - Tool that generates the elements / services dependency graph for the required adaptation . As HW / SW / Functional interfaces are modeled in the same way ...
265. lappuse
invalid elements / services using a colored graph technique as described in [ 16 ] . It uses two mutually recursive functions . The first one treats elements and the other one services . For each service , the SDG generator searches an ...
invalid elements / services using a colored graph technique as described in [ 16 ] . It uses two mutually recursive functions . The first one treats elements and the other one services . For each service , the SDG generator searches an ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
31 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx