CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.3. rezultāts no 79.
45. lappuse
... efficiently in most embedded applications . We design an efficient cache a configurable instruction cache that can be tuned to utilize the cache sets efficiently for a particular application such that cache memory is exploited more ...
... efficiently in most embedded applications . We design an efficient cache a configurable instruction cache that can be tuned to utilize the cache sets efficiently for a particular application such that cache memory is exploited more ...
49. lappuse
... efficient cache consumes less energy than that of a conventional direct mapped cache . Compared with the conventional two - way set associative caches , which have almost the same miss rate as our efficient cache , the energy ...
... efficient cache consumes less energy than that of a conventional direct mapped cache . Compared with the conventional two - way set associative caches , which have almost the same miss rate as our efficient cache , the energy ...
50. lappuse
... efficient cache The design of the efficient cache requires simulating the applications beforehand to determine what is the best index decoding schemes that can be implemented by the configurable decoder . However , different input data ...
... efficient cache The design of the efficient cache requires simulating the applications beforehand to determine what is the best index decoding schemes that can be implemented by the configurable decoder . However , different input data ...
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx