CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.3. rezultāts no 80.
110. lappuse
... dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off - chip access to on - chip computation times . In IEEE Transactions on Computer - Aided Design of Integrated Circuits and ...
... dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off - chip access to on - chip computation times . In IEEE Transactions on Computer - Aided Design of Integrated Circuits and ...
113. lappuse
... dynamic bounds ( see Figure 2 ) . The static bounds are obtained at the design time using an offline analysis and are then used by the scheduler at runtime . In this sense they are similar to conventional workload characterizations such ...
... dynamic bounds ( see Figure 2 ) . The static bounds are obtained at the design time using an offline analysis and are then used by the scheduler at runtime . In this sense they are similar to conventional workload characterizations such ...
322. lappuse
... DYNAMIC PHASE CLASSIFICATION In this section we discuss phase behavior , code signatures , and we explain how the dynamic phase classifier works as the program executes . Our work builds upon program phase analysis techniques presented ...
... DYNAMIC PHASE CLASSIFICATION In this section we discuss phase behavior , code signatures , and we explain how the dynamic phase classifier works as the program executes . Our work builds upon program phase analysis techniques presented ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx