CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 50.
179. lappuse
... domain on each processor , so that the basic - function domain is separated physically from the other domains . This platform can confine the influence of any downloaded application to the single domains on which it is to be executed ...
... domain on each processor , so that the basic - function domain is separated physically from the other domains . This platform can confine the influence of any downloaded application to the single domains on which it is to be executed ...
180. lappuse
... Domain Communication ( IDC ) , of viruses or other malicious attacks . 2.2.1 XIP Kernels for OS - level Separation ... domain . For example , the policy for the base domain may be relaxed , the policy for the trusted domain may have ...
... Domain Communication ( IDC ) , of viruses or other malicious attacks . 2.2.1 XIP Kernels for OS - level Separation ... domain . For example , the policy for the base domain may be relaxed , the policy for the trusted domain may have ...
182. lappuse
... domain without any performance influence to the base domain . Further , the security level is not high enough , since a process might be able to waste a lot of CPU time by the execution code of busy - wait loop and the process could ...
... domain without any performance influence to the base domain . Further , the security level is not high enough , since a process might be able to waste a lot of CPU time by the execution code of busy - wait loop and the process could ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx