CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 74.
210. lappuse
... distributed 3D - FFT implementations use a “ slab " decomposition in which the three dimensional FFT mesh is parti- tioned along a single mesh coordinate axis so that each node has a " slab " of the entire FFT mesh . This allows use of ...
... distributed 3D - FFT implementations use a “ slab " decomposition in which the three dimensional FFT mesh is parti- tioned along a single mesh coordinate axis so that each node has a " slab " of the entire FFT mesh . This allows use of ...
211. lappuse
... distributed data transpose required by the 3D - FFT . For the transpose , in most regimes , the execution time is limited by the bisectional bandwidth of the machine , therefore a fixed size FFT will speed up as p2 / 3 where p is the ...
... distributed data transpose required by the 3D - FFT . For the transpose , in most regimes , the execution time is limited by the bisectional bandwidth of the machine , therefore a fixed size FFT will speed up as p2 / 3 where p is the ...
320. lappuse
... distributed , loosely connected embedded systems . Scripting represents one of the most promising solution and has demonstrated compelling advantages in general - purpose computing . The interactive nature not only short- ens ...
... distributed , loosely connected embedded systems . Scripting represents one of the most promising solution and has demonstrated compelling advantages in general - purpose computing . The interactive nature not only short- ens ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
31 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx