CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.3. rezultāts no 53.
95. lappuse
... device were deferred until this time , there would be no guarantee of receiving the requested mem- ory . Therefore , the compressed swap device starts with a small , predefined size but expands and contracts dynamically . Note that ...
... device were deferred until this time , there would be no guarantee of receiving the requested mem- ory . Therefore , the compressed swap device starts with a small , predefined size but expands and contracts dynamically . Note that ...
96. lappuse
... device or decompressing a block that is read from the device , ( 2 ) al- locating memory for a compressed block or locating a compressed block with an index number , ( 3 ) managing the mapping table , and ( 4 ) merging free slots when ...
... device or decompressing a block that is read from the device , ( 2 ) al- locating memory for a compressed block or locating a compressed block with an index number , ( 3 ) managing the mapping table , and ( 4 ) merging free slots when ...
97. lappuse
... device 4.2 . CRAMES and RAM Disk Comparison Figure 5 illustrates the logical structure and request handling of a RAM disk4 . As shown in the figure , the virtually contiguous mem- ory space in RAM disk is divided into fixed - size ...
... device 4.2 . CRAMES and RAM Disk Comparison Figure 5 illustrates the logical structure and request handling of a RAM disk4 . As shown in the figure , the virtually contiguous mem- ory space in RAM disk is divided into fixed - size ...
Saturs
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A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx