CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 68.
131. lappuse
... developed . In this work , FV16 is developed in three steps : ( 1 ) Identify recurring and intensively used operations , for which special hardware modules are constructed ; ( 2 ) Platform design : create interconnect , storage and ...
... developed . In this work , FV16 is developed in three steps : ( 1 ) Identify recurring and intensively used operations , for which special hardware modules are constructed ; ( 2 ) Platform design : create interconnect , storage and ...
211. lappuse
... developed in support of and in conjunc- tion with the Blue Gene science program . As part of that effort we have developed a new variant of spatial decomposition for n - body simulations that permits effective load balancing of real ...
... developed in support of and in conjunc- tion with the Blue Gene science program . As part of that effort we have developed a new variant of spatial decomposition for n - body simulations that permits effective load balancing of real ...
267. lappuse
... developed and advocated as a standard . In this paper , a specific implementation of the TTL interface named ITCP ( Inter - Task Communication Protocol ) is presented . ITCP is well suited for both hardware and software implementations ...
... developed and advocated as a standard . In this paper , a specific implementation of the TTL interface named ITCP ( Inter - Task Communication Protocol ) is presented . ITCP is well suited for both hardware and software implementations ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx