CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.3. rezultāts no 35.
50. lappuse
... depends on input data sets . To determine the prevalence of this situation , we simulated all the benchmarks using a secondary input data set that comes with Mediabench . We haven't found that the best index decoding has been changed ...
... depends on input data sets . To determine the prevalence of this situation , we simulated all the benchmarks using a secondary input data set that comes with Mediabench . We haven't found that the best index decoding has been changed ...
150. lappuse
... depends on the status of that element . In addition , each resource type R ' can be in one of its Z different modes . Resource modes depend on the processing activity of a re- source and its present power mode status . Every element of ...
... depends on the status of that element . In addition , each resource type R ' can be in one of its Z different modes . Resource modes depend on the processing activity of a re- source and its present power mode status . Every element of ...
242. lappuse
... depends on the spatial locality of memory accesses and the average size of basic blocks in the simulated program . Future work will focus on application of these techniques on further real - world processors . 6. Reference [ 1 ] Achim ...
... depends on the spatial locality of memory accesses and the average size of basic blocks in the simulated program . Future work will focus on application of these techniques on further real - world processors . 6. Reference [ 1 ] Achim ...
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Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx