CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 41.
10. lappuse
... dependent modifications to the original C source . Intrinsics which eliminated these barriers have been explored [ 8 ] . The main technique is to represent the operation in the intermediate representation of the compiler . With the ...
... dependent modifications to the original C source . Intrinsics which eliminated these barriers have been explored [ 8 ] . The main technique is to represent the operation in the intermediate representation of the compiler . With the ...
62. lappuse
... dependent on the tasks themselves just as on the DSPs . Starting and continuing tasks has short response times because no acknowledgement is needed from either the tasks or the sched- ulers . A ttlTaskStart and ttlTaskContinue call uses ...
... dependent on the tasks themselves just as on the DSPs . Starting and continuing tasks has short response times because no acknowledgement is needed from either the tasks or the sched- ulers . A ttlTaskStart and ttlTaskContinue call uses ...
244. lappuse
... dependent on the used JVM . Other authors have addressed the opti- misation problem at a higher level , by implementing Java methods in reconfigurable hardware [ 5 , 8 ] . However , these solutions are usually dependent on the ...
... dependent on the used JVM . Other authors have addressed the opti- misation problem at a higher level , by implementing Java methods in reconfigurable hardware [ 5 , 8 ] . However , these solutions are usually dependent on the ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
31 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx