CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 47.
47. lappuse
... decoder subarray decoder ( a ) ( b ) TILI Figure 2 : The organization of an efficient cache . row of the decoder may need don't care functions . The V1 , i = 1 , 2 , ... 8 , are valid signals of the configurable decoder . When V1 , V3 ...
... decoder subarray decoder ( a ) ( b ) TILI Figure 2 : The organization of an efficient cache . row of the decoder may need don't care functions . The V1 , i = 1 , 2 , ... 8 , are valid signals of the configurable decoder . When V1 , V3 ...
48. lappuse
... decoder Determine the best decoder configuration 8 0.86 0.87 0.96 NO D $ through the proposed 16 0.93 0.95 1.13 NO SOC algorithm Table 1 : Access Time of our proposed cache . subarray and three fourths of the address space to the ...
... decoder Determine the best decoder configuration 8 0.86 0.87 0.96 NO D $ through the proposed 16 0.93 0.95 1.13 NO SOC algorithm Table 1 : Access Time of our proposed cache . subarray and three fourths of the address space to the ...
59. lappuse
... decoder c4 t3 17 Output Fork c5 to D / A Figure 3. Use Case 2 In use case 3 , two different MP3 files are decoded and played back on two sets of stereo speakers . The task graph is organized as two independent copies of use case 1. Use ...
... decoder c4 t3 17 Output Fork c5 to D / A Figure 3. Use Case 2 In use case 3 , two different MP3 files are decoded and played back on two sets of stereo speakers . The task graph is organized as two independent copies of use case 1. Use ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
31 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx