CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 42.
21. lappuse
... datapath of the architecture is fully allocated before scheduling and binding . We compile a C program directly to the datapath and generate the controller . We can support the entire ANSI C syntax because the datapath can be as complex ...
... datapath of the architecture is fully allocated before scheduling and binding . We compile a C program directly to the datapath and generate the controller . We can support the entire ANSI C syntax because the datapath can be as complex ...
26. lappuse
... datapath of NM1 by adding one more ALU and 2 more register file read ports . Because of their similar datapath , the clock periods of these architectures are similar . The second , third and forth columns in Table 2 show the execution ...
... datapath of NM1 by adding one more ALU and 2 more register file read ports . Because of their similar datapath , the clock periods of these architectures are similar . The second , third and forth columns in Table 2 show the execution ...
134. lappuse
... Datapath Design 3.3.4 Branch Instructions Since loops are used extensively in the fuzzy vault scheme , branch instructions , including non - conditional jump and conditional jump , are designed to support decision - making and control ...
... Datapath Design 3.3.4 Branch Instructions Since loops are used extensively in the fuzzy vault scheme , branch instructions , including non - conditional jump and conditional jump , are designed to support decision - making and control ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
31 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx