CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 24.
321. lappuse
... cycle accurate simulation . In this paper we propose a method to provide Cycle - Close Traces of cycle - level statistics for the complete execution of program in orders of magnitude less time than perform- ing full cycle accurate ...
... cycle accurate simulation . In this paper we propose a method to provide Cycle - Close Traces of cycle - level statistics for the complete execution of program in orders of magnitude less time than perform- ing full cycle accurate ...
323. lappuse
... cycle accurate simulation sample . Before each interval is executed , we predict which phase the interval will belong to . To guide sampling , we keep track of which phase IDs already have a representative sample with a flag in the ...
... cycle accurate simulation sample . Before each interval is executed , we predict which phase the interval will belong to . To guide sampling , we keep track of which phase IDs already have a representative sample with a flag in the ...
324. lappuse
... cycle latency 64 cycle round trip access in - order issue of up to 1 operation per cycle 1 integer ALU , 1 - FP adder , 1 integer and 1 FP MULT / DIV Table 1 : Baseline Simulation ... accurate simulation is obtained by running each benchmark ...
... cycle latency 64 cycle round trip access in - order issue of up to 1 operation per cycle 1 integer ALU , 1 - FP adder , 1 integer and 1 FP MULT / DIV Table 1 : Baseline Simulation ... accurate simulation is obtained by running each benchmark ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx