CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 85.
145. lappuse
... cores , Use power simulation tools with the parasitics , to generate power characterization information Create macromodels based on various IP core parameters : Parameters can be bit - width , switching activity of data , buffer size O ...
... cores , Use power simulation tools with the parasitics , to generate power characterization information Create macromodels based on various IP core parameters : Parameters can be bit - width , switching activity of data , buffer size O ...
188. lappuse
... core executing the DES encryption . From these results , we can conclude that the current values and the current variation levels within an ARM7TDMI processor core can be reduced by voltage scaling and by reducing the switching activity ...
... core executing the DES encryption . From these results , we can conclude that the current values and the current variation levels within an ARM7TDMI processor core can be reduced by voltage scaling and by reducing the switching activity ...
210. lappuse
... core mode except for the " Real Space ” data which had to be taken in single core mode because the trace facility only works on “ Core 0 " and in dual core mode the real space non - bond interactions are handled on " Core 1 " . Node A ...
... core mode except for the " Real Space ” data which had to be taken in single core mode because the trace facility only works on “ Core 0 " and in dual core mode the real space non - bond interactions are handled on " Core 1 " . Node A ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
Autortiesības | |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx