CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.3. rezultāts no 22.
134. lappuse
... Coprocessor Partitioning OR Rn , Rm Rn Rm Rm 0x09RnRm Driver Software AND Rn , Rm Rn & RmRm 0x28RnRm Control Flow Design Coprocessor Program in C code Datapath Design 3.3.4 Branch Instructions Since loops are used extensively in the ...
... Coprocessor Partitioning OR Rn , Rm Rn Rm Rm 0x09RnRm Driver Software AND Rn , Rm Rn & RmRm 0x28RnRm Control Flow Design Coprocessor Program in C code Datapath Design 3.3.4 Branch Instructions Since loops are used extensively in the ...
297. lappuse
... coprocessor . We contrast the acceleration by implement- ing the critical segment as two different coprocessors and a set of customized instructions . The two different coprocessor approaches are : a high - level synthesis ( HLS ) ...
... coprocessor . We contrast the acceleration by implement- ing the critical segment as two different coprocessors and a set of customized instructions . The two different coprocessor approaches are : a high - level synthesis ( HLS ) ...
301. lappuse
... coprocessor requires them . These calculations are required due to the fact that it is not pos- sible to break the loop functionality of the coprocessor using the HLS framework . Such tasks would be more complicated in situa- tions ...
... coprocessor requires them . These calculations are required due to the fact that it is not pos- sible to break the loop functionality of the coprocessor using the HLS framework . Such tasks would be more complicated in situa- tions ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx