CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 55.
119. lappuse
... configuration Final configuration Energy the energy consumption of the system , but can change its execution time by adapting the clock frequency . The cost of introducing both of these knobs is very limited . In some recent memory ...
... configuration Final configuration Energy the energy consumption of the system , but can change its execution time by adapting the clock frequency . The cost of introducing both of these knobs is very limited . In some recent memory ...
120. lappuse
... configuration , switching it to high - speed will just waste energy for no time gain . This makes the problem much more tractable than it originally appears and it is enabled by the fact that the energy / delay configuration options per ...
... configuration , switching it to high - speed will just waste energy for no time gain . This makes the problem much more tractable than it originally appears and it is enabled by the fact that the energy / delay configuration options per ...
275. lappuse
... configuration is an assignment with maps v : T P and v : L - PUC . Valid configurations resulting from the task allocation problem have the following characteristics : ( a ) Each task tЄ T is assigned to a single processor p € P. ( b ) ...
... configuration is an assignment with maps v : T P and v : L - PUC . Valid configurations resulting from the task allocation problem have the following characteristics : ( a ) Each task tЄ T is assigned to a single processor p € P. ( b ) ...
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx