CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 38.
91. lappuse
d without compression CRAMES : Compressed RAM for Embedded Systems Lei Yang +. Processor Step 1 Step 2 Step 3 Step 4 ... compression Figure 4 : The data block placement generated with compres- sion and without compression . Note that both ...
d without compression CRAMES : Compressed RAM for Embedded Systems Lei Yang +. Processor Step 1 Step 2 Step 3 Step 4 ... compression Figure 4 : The data block placement generated with compres- sion and without compression . Note that both ...
94. lappuse
... Compression Ratio gives a measure of the compression achieved by one compression algorithm on a page of data . It is compressed page size divided by original page size . Table 1 : Memory overhead of evaluated compression algorithms ...
... Compression Ratio gives a measure of the compression achieved by one compression algorithm on a page of data . It is compressed page size divided by original page size . Table 1 : Memory overhead of evaluated compression algorithms ...
95. lappuse
Table 1 : Memory overhead of evaluated compression algorithms Compression Decompression bzip2 7600 kB 3700 kB 2116 256 KB 44 KB LZO 64 KB 0 LZRWI - A 16 KB 16 KB RLE 0 0 RAM device does not have a fixed size ; instead , it is a linked ...
Table 1 : Memory overhead of evaluated compression algorithms Compression Decompression bzip2 7600 kB 3700 kB 2116 256 KB 44 KB LZO 64 KB 0 LZRWI - A 16 KB 16 KB RLE 0 0 RAM device does not have a fixed size ; instead , it is a linked ...
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx