CODES+ISSSACM Press, 2005 |
No grāmatas satura
1.–3. rezultāts no 64.
144. lappuse
... ( Complex ) Figure 3 , shows the overall structure of the HTLP - tree structure . It is organized into four different ... complex transactions . A complex transaction like a burst read or write consists of a set of simple individual ...
... ( Complex ) Figure 3 , shows the overall structure of the HTLP - tree structure . It is organized into four different ... complex transactions . A complex transaction like a burst read or write consists of a set of simple individual ...
202. lappuse
... complex than DNA microarrays , which are representative of early biochips . Integrated functions include microfluidic assay operations and detection , as well as sample pre - treatment and preparation . So far there are two different ...
... complex than DNA microarrays , which are representative of early biochips . Integrated functions include microfluidic assay operations and detection , as well as sample pre - treatment and preparation . So far there are two different ...
328. lappuse
... complex work by the verification engineer on tuning the acceleration algorithms to the specific design . In the present paper , we propose a simple method , based on redundant stimuli filtering . It allows reducing execution time of ...
... complex work by the verification engineer on tuning the acceleration algorithms to the specific design . In the present paper , we propose a simple method , based on redundant stimuli filtering . It allows reducing execution time of ...
Saturs
Keynote | 3 |
A Core Flight Software System | 13 |
A CycleAccurate Compilation Algorithm for Custom Pipelined Datapaths | 21 |
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abstraction algorithm allocation analysis application approach architecture benchmarks binary biochips buffer byte cache channel chip circuit clock communication compiler components compression Computer configuration constraints copies coprocessor core CRAMES cycle cycle accurate simulation data block decoder digital microfluidic DVFS dynamic Echo instructions EEMBC efficient embedded systems energy consumption execution FPGA function graph hardware hash IEEE implementation input instruction-set interface iteration latency loop mapping marked graph memory accesses methodology microblaze microfluidic minimal minterms minterms module multiplier multiprocessor node on-chip operations optimal output overhead packet parallel parameters partition performance pipeline platform port power consumption Proc processor proposed reconfigurable reduce resource router runtime samples scheduling SECTAG Section SELinux simulation space specific speedup switch synchronization synthesis SystemC Table target task techniques tion transaction universal hash functions vector VLIW voltage WCET Xilinx